In general, capacitor structures with very high capacitor density have become an issue for applications such as power source decoupling. For such decoupling applications, surface-mounted capacitors are commonly implemented at the printed board level. These capacitors are connected to the power source in parallel with an electronic circuit which is power-fed by the power source. However, significantly long electrical connections are necessary in such implementations between the surface-mounted capacitors and the power source, and also to the circuit, and these connections produce significant equivalent serial inductance. These implementations are therefore inappropriate for efficient decoupling when high rejection is desired.
Silicon-embedded capacitor structures are technology alternative to the surface-mounted capacitors, and they do not require long electrical connections. Then the equivalent serial inductance is no longer an issue for power source decoupling applications, but the silicon-embedded capacitor structures exhibit high equivalent serial resistance, especially for 3D-capacitor structures. Indeed, the 3D-capacitor structures implement electrode layers which are deposited within trenches, and which then have features including: (1) the electrode design within the trenches leads to flow distances for the electrical charges in the electrodes which are quite long; (2) the electrode layers are thin for avoiding clogging of the trenches during deposition of each electrode layer; and (3) the deposition processes that are implemented for in-trench deposition of the electrodes are limited to electrode materials which do not have very high values for electrical conductivity.
These features contribute to increase the equivalent serial resistance. They are especially critical for the second electrode, also called intermediate electrode when a double capacitor layer stack is used inside and between the trenches. Indeed, although producing higher values for the capacitor density, double capacitor layer stacks lead simultaneously to higher values for the equivalent serial resistance, in particular due to the small thickness and limited conductivity of the layer which forms the second electrode.
Starting from this situation for 3D-capacitor structures based on double capacitor layer stacks, it has been implemented arranging a metal wiring network in parallel with the second electrode, and providing electrical contacts from this wiring network to the second electrode according to a distributed design, so as to avoid long-distance flow for the electrical charges within the second electrode. However, providing a plurality of electrical contacts to the second electrode of a 3D-capacitor structure based on a double capacitor layer stack may be a difficult issue. It requires removing the third electrode layer at the locations of the contact areas. But because the double capacitor layer stack conforms to the trench design, short-circuits between the second and the third electrodes may occur near the top edges of the trenches. For avoiding such short-circuits, the electrical contacts to the second electrode layer may be located in circuit parts which are devoid of trenches. The layout of the capacitor structure in these circuit parts is then no longer three-dimensional, i.e. it is comprised of electrode layers which are parallel to the top face of the circuit substrate. It is then easy to remove the third electrode within these circuit parts and produce electrical contacts to the second electrode, while ensuring that no short-circuit between the second and the third electrodes occur.
However, providing circuit parts where the electrode layers are parallel to the substrate top face leads to decrease the capacitor density as compared to 3D-capacitor structures.